The integrity requirements for personal computer systems have grown rapidly in the past few years. At the present time, newer operating systems and applications require a great deal of memory, and the amount of memory which can be accommodated in personal computer systems continues to increase rapidly. Such personal computer systems have in the past typically been provided only with the capability of writing and checking parity--if even that. In such a case of parity, if an odd number of bits of memory is corrupted, the bad parity condition will be flagged, and generally the system will halt when the error is detected. This poses a significant problem since users can ill afford to have periodic system crashes and/or loss of data, and as the amount of memory increases, the possibility of such data corruption increases significantly. In the case of systems which do not write and check parity, corrupted data can cause malfunction of the system. Moreover, with the advent of large applications which normally require large amounts of memory, these are the most exposed to such a crash and data corruption.
As indicated above, until very recently most conventional current low end personal computer systems contained at best only parity SIMMs which can detect an odd number of bit errors, but cannot correct such errors. Moreover, a parity function cannot detect double or other even number bit errors.
One solution which has been proposed to eliminate system crash or corruption of data due to single-bit errors is to provide error correction code for use in computer systems which do not have error correction code capabilities internal thereto. Typically, this error correction code allows for the detection of most double-bit errors and the correction of all single-bit errors. These schemes are a significant improvement over purely parity SIMMs. One technique for utilizing ECC is the so-called 32/7-bit ECC algorithm. This ECC algorithm requires 7 check bits for each double word (i.e., 4 bytes or 32 bits, thus the designation 32/7). This results in a 39-bit wide memory SIMM required for each double word and associated 7-check bits (32 data bits+7 check bits). Thus, the widely-used 36-bit wide memory SIMM is not available to be used, although this is a conventional and popular size SIMM and is used with double words containing only parity bits which requires only 36 bits (32 data bits plus 4 parity bits). More importantly, many systems do not have wait states programmed either in the system or in the bus interface circuit, and thus read-modify-write (RMW) operations cannot be performed because of the additional time required from RMW. RMW is required when less than all of the bytes of a multiple data byte word are being written For example, if only one byte of a four-byte data word is being rewritten, a RMW cycle must be performed to recalculate and generate new check bits or the check bits associated with the entire 32 bits of data will be in error.
Thus, in the case of systems configured to write less than all the bytes of a multiple byte data word (which is typical) and where ECC has been attempted, the systems or at least the interface circuit has to be modified to provide for the necessary delays to perform a RMW cycle when the ECC algorithm uses all of the data bits and generate check bits such as in the 32/7 bit ECC algorithm.
Thus, it is an object of the present invention to provide an improved ECC on SIMM which allows writing of single byte words and which SIMMs are compatible with systems which do not have wait states necessary for RWM cycles and wherein parity of the written data is checked. If bad parity is detected such bad parity is flagged on the read cycle.